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[VHDL-FPGA-Verilog] State_Machine

Description: 状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state machine.
Platform: | Size: 1551360 | Author: baoguocheng | Hits:

[matlab] 2moreqamcodes

Description: the code is about ML detector of mimo technology ,,,,we need of vhdl code for all detectors
Platform: | Size: 5120 | Author: bhagyalaxmi | Hits:

[VHDL-FPGA-Verilog] s101

Description: 用VHDL语言，设计一个“101”序列检测器，双过程描述编写-VHDL language, to design a dual procedure describes the preparation of "101" sequence detector.
Platform: | Size: 173056 | Author: henry | Hits:

[VHDL-FPGA-Verilog] EDA1

Description: 用VHDL编程实现序列信号发生器与检测器设计和数字钟设计-VHDL programming sequence signal generator and detector design and the design of the digital clock
Platform: | Size: 260096 | Author: 高华 | Hits:

[VHDL-FPGA-Verilog] p_dect--5

Description: 奇偶检测器 vhdl实现 quartus编译通过-Parity detector the vhdl realize quartus compiled by
Platform: | Size: 393216 | Author: 蒲瑞瑞 | Hits:

[VHDL-FPGA-Verilog] EDAexp4

Description: FPGA环境下，用VHDL语言实现序列脉冲器和检测器。-FPGA environment, the use of the VHDL sequence of pulses and detector.
Platform: | Size: 15360 | Author: 吴霏羽 | Hits:

[VHDL-FPGA-Verilog] aa

Description: 这个程序就是序列检测器的vhdl实现，真麻烦啊-This program is the sequence detector vhdl achieve real trouble
Platform: | Size: 1024 | Author: zhangzhen | Hits:

[VHDL-FPGA-Verilog] check

Description: 这是一个检测器，功能是可以检测输入信号里面“1111”序列的vhdl程序。-This is a detector, the function is the sequence of " 1111" of the input signal which can be detected vhdl procedures.
Platform: | Size: 3072 | Author: 仝侨 | Hits:

[VHDL-FPGA-Verilog] serial1

Description: 基于VHDL语言实现的序列检测器，包含按键防抖动功能的实现。-Sequence detector based on the VHDL language, containing the button shake function to achieve.
Platform: | Size: 1024 | Author: momo | Hits:

[Algorithm] even_detector_file_based_stimuli

Description: even detector based stmiulde and vhdl code
Platform: | Size: 2048 | Author: aasad | Hits:

[Other] 11

Description: VHDL序列检测器，使用了EDA课程里面用到的状态机.-VHDL sequence detector, the use of EDA curriculum used inside the state machine.
Platform: | Size: 1024 | Author: 蒋峰 | Hits:

[VHDL-FPGA-Verilog] SCHK

Description: ise13.2环境下VHDL编写的8位序列检测器+仿真波形-ise13.2 environment in VHDL 8 sequence detector+ simulation waveforms
Platform: | Size: 479232 | Author: 初末 | Hits:

[VHDL-FPGA-Verilog] basic_1

Description: vhdl 语言实现序列检测器 -vhdl language sequence detector vhdl language sequence detector
Platform: | Size: 1024 | Author: lixi | Hits:

[VHDL-FPGA-Verilog] seq_detector

Description: 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test source program.
Platform: | Size: 1024 | Author: 10086 | Hits:

[Other] checkfor1101

Description: 1101序列检测器，VHDL编写，外部输入任意序列，一旦检测到1101就亮led提示。-1101 sequence detector, VHDL prepared, external input arbitrary sequence, once detected 1101 bright LED tips.
Platform: | Size: 110592 | Author: Ronge | Hits:

[Other] 6_bit_prime_detector

Description: 6 bit prime detector vhdl
Platform: | Size: 1024 | Author: Jeong Hyeock Jin | Hits:

[VHDL-FPGA-Verilog] xuliejiancejisuanqikongzhiqi

Description: VHDL序列检测器，计算器，控制器编码以及实现方法。-VHDL sequential detector, calculator, controller and its implementation method.
Platform: | Size: 51200 | Author: 景生 | Hits:

[VHDL-FPGA-Verilog] code

Description: 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, digital locks, four have signed division synchronous FIFO, DPLL design and Cordic algorithm. For beginners VHDL great reference value.
Platform: | Size: 20480 | Author: 朱召宇 | Hits:

[VHDL-FPGA-Verilog] examples

Description: Code on Debouncer, ripple carry adder, Sequence detector, huffmann encoder and some more examples in VHDL
Platform: | Size: 6736896 | Author: SUDHIR | Hits:

[VHDL-FPGA-Verilog] Lab3

Description: Sequential binary Message detector Objectives 1. Working with finite state machines. 2. Defining user types in VHDL
Platform: | Size: 187392 | Author: Amr | Hits:
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